PICMOS - Photonic Interconnect Layer on CMOS by wafer- scale integration Motivation

For future generation electronic circuits, a severe bottleneck is expected on the global interconnect level. With decreasing device dimensions, it is increasingly difficult to keep propagation delays acceptable and even with the most optimistic estimates for conductor resistivity and dielectric permittivity, the performance roadmap projected by the ITRS will not be met. Therefore there is a need for radically different interconnect approaches and one of the most promising solutions is the incorporation of an optical interconnect layer on top of or in between the classical Cu-interconnect layers of future microprocessor chips. This optical interconnect layer could allow for an enormous bandwidth increase, for immunity to electromagnetic noise, for a decrease in the power consumption, the possibility for synchronic operation within the circuit and with other circuits and for a reduced immunity to temperature changes.